FPGA based, Xylinx Spartan 3
16 channels, 8bit samples, 16/24bit output
build-in 2 Pokey chips cores and simple Covox interface for compatibility with existing software
Internal version sits in Pokey soket, but doesn't replace it
External version available (Cartridge), but limited to SoundBoard specific functionality (NO POKEY support in this version)

Base address: D2C0

offset    name        bits    description
0    SBchnAdr low    24    Base address of sample for playback
1    SBchnAdr mid
2    SBchnAdr high
3    SBchnLen low    16    Sample lenght
4    SBchnLen high
5    SBchnRep low    16    Sample repeat (offset to be loaded
6    SBchnRep high        when phase accumulator reaches sample lenght
7    SBchnFreq low    16    constat to be added to phase accumulator
8    SBchnFreq high
9    SBchnVol     8(6)    volume for given channel (left aligned 6 bit)
A    SBchnPan    8(6)    panning control for given channel (la 6 bit)
B    SBchnAtt    8    Attack rate for ADSR envelope generator
C    SBchnDec    8    Decay rate for ADSR envelope generator
D    SBchnSust    8    Sustain volume level for ADSR envelope generator
E    SBchnRel    8    Release rate for ADSR envelope generator
F    SBchnCtrl    3    Channel Control (see below)
10    SBsmAdr low    24    Base address of memory pointer for sample load
11    SBsmAdr    mid
12    SBsmAdr low
13    SBsmDta        8    Data register for sample load
14    SBchnNo        4    Channell number selector (0-15 selects apriopriate channell)


bitfields for SBchnCtrl:
bit    name        description
0    DMAEN        when 1 enables DMA for given channel
      when 0 disables DMA for given channel
1    Gate        when 1 ADSR generator stops at Sustain
            when 0 ADSR generator continues with Release
2    ADSREN        when 1 enables ADSR generator
            when 0 ADSR generator is bypassed
3    FMMOD        when 1 channell becomes modulator for channel n+4
            ie Channel 0 becomes modulator for channel 4
            ch. 1 -> ch. 5
            etc
            in this mode channel output is treated as follows
    Let Channell 0 is called Modulator and Channell 8 becomes Carrier, then
    Carrier.frequency=Modulator.Sample_value*(Modulator.ADSR*Modulator.Volume)
    output value is 16 bit, so Volume*ADSR can be treated as modulation depth
    only 8 upper bits of Volume*ADSR product are taken into consideration

Base clock for each channell is phi2
Memory size is 1024kB, so only 20 of 24 bits of address registers are valid
after reset all SBchnCtrl registers are zeroed, rest is undetermined
CAUTION! Playing of sample starts from beginning only when at first channel 
will be disabled then enabled; enabling yet enabled channel don't go.